Changes

* Rise and delay time was increased

====Solution====

* High speed logic circuit family in which the rise and delay times of the gate are minimized. In other words, the internal delay of the gate in providing a logic output signal which accurately reflects the state of the logic input signals must be minimized.

* It has been found, according to the invention that when the geometry of the gating FETs are arranging as described above, the internal delay time of the logic gate is dramatically decreased thereby improving the speed of the gate while still insuring reliable logic switching.