Difference between revisions of "Invalidation of a semiconductor patent"

Latest revision as of 14:32, 14 August 2009

Complementary logic input parallel (CLIP) field effect transistor (FET) logic circuit

Problems and solutions in the prior art

Problem

• Serial connection of the load transistors in conventional CMOS logic gates reduces the toggle rate or switching speed of the gate and also reduces the number of inputs which may be applied to the gate (referred to as "fan-in").

Solutions

• To overcome these problems an "all parallel" CMOS gate design has heretofore been proposed. Here serial load transistors are replaced by a first load which may be an MOS transistor or a resistor, and a second load comprising an MOS transistor having opposite conductivity type from the driver stage transistors.

• A high speed, high density low power dissipation complementary FET logic circuit is disclosed, in which the voltage transfer function of the logic gate's complementary FET inverter output stage is deliberately skewed to dramatically decrease the lift-off interval for the logic gate and thereby dramatically increase the speed of the gate

Problems and solutions for the present invention (CLIP AND & OR logic circuits)

CLIP AND & OR logic circuits according to the invention

Problem - 1

• Rise and delay time was increased

Solution

• High speed logic circuit family in which the rise and delay times of the gate are minimized. In other words, the internal delay of the gate in providing a logic output signal which accurately reflects the state of the logic input signals must be minimized.
• It has been found, according to the invention that when the geometry of the gating FETs are arranging as described above, the internal delay time of the logic gate is dramatically decreased thereby improving the speed of the gate while still insuring reliable logic switching.
• Geometry of gating FET's: logic gate 10 also includes a gating stage 13 including a pair of gating transistors 13a, 13b serially connected between the common output 16 and the second reference potential (ground). As illustrated in FIG. 3, two gating transistors are used, however any number of gating transistors may be used. Control electrodes 18a and 18b are connected to the control electrodes 12f and 12e of transistors 11f and 11e respectively. Accordingly, gating transistors 13 are turned on when transistors 11e and 11f are turned off. It will be understood by those having skill in the art that control electrodes 18 may be connected to any of control electrodes 12.
• The dimensions of the gating FETs are controlled relative to the dimensions of the driving stage FETs to provide a high speed logic circuit

Problem - 2

• Lower saturation current and corresponding lower carrier mobility of P-channel device compared to N-channel limits the overall speed of the logic gate

Solution

• Provide a high speed complementary all-parallel FET logic family, the performance of which is not limited by the inherently lower saturation current and carrier mobility of P-channel FET devices.
• Speed of the CLIP logic circuits described above is further increased by including germanium in the channels of the P-channel FETs, to thereby increase the carrier mobility in the P-channel FETs. The N-channel FETs are free of germanium so that the carrier mobility of only the P-channel devices is increased. In a preferred embodiment up to 38 atomic percent of the silicon P-channel is germanium, to thereby substantially equalize the carrier mobility of the N-channel FETs and the P-channel FETs. Accordingly, the saturation current limitation of P-channel FETs is reduced and may even be eliminated. It will be understood by those having skill in the art germanium may be included in P-channel FETs of all complementary FET logic circuits to thereby equalize the carrier mobilities in the P and N-channel devices and thereby increase the logic circuit speed.

Problem - 3

• Internal capacitance of the logic gate also is a major roadblock in increasing its speed. The internal capacitance of the gate also typically limits the number of logic inputs which can be handled by a single gate

Solution

• Provide a high speed complementary all-parallel FET logic family which exhibits low internal capacitance so that large numbers of logic inputs may be handled by a single gate.
• Internal capacitance of the CLIP logic circuits is decreased by using common diffusion regions in the integrated circuit, for pairs of driving stage transistors. The use of the common diffusion region between pairs of FET driving transistors reduces the capacitive loading of the common output by a factor of two thereby further increasing the switching speed of the CLIP logic circuits
• Shared diffusion technique may be used for any all-parallel logic circuit to reduce diffusion capacitance by a factor of two

Other circuits

Clocked CLIP Logic Gates

• In the clocked AND gate, the output 17 is high when all of the gates 12a-12e are high and the clock is high.
• In the clocked OR gate, when a clock pulse is applied, clocking FET 21 is turned on and gating FET 13 is turned off. If any one or more of the logic control gates 12a-12f are up then the output of inverter 14 rapidly rises to supply potential Vdd. When the clock pulse drops to ground potential, clocking FET 21 is turned off and gating FET 13 is turned on. When this occurs, the potential of the common output 16 rises rapidly to supply potential Vdd and the output 17 of the inverter 14 rapidly drops to ground potential.

Latching Clocked CLIP Logic Gates

• Latching Clocked CLIP AND gate - Latching FET 23 ensures that the output 17 of complementary inverter 14 remains unchanged during the clock period, regardless of any change in voltage at the inputs 12a-12e.
• Latching Clocked CLIP OR gate -
  • The output 17 of complementary inverter 14 is fed back to the gate 24a of the latching FET 23a.
  • During the clock pulse interval, if any one of the driving stage transistors 11a-11e is turned on by virtue of its control 12a-12f being at supply potential, the output 17 of the complementary inverter 14 is switched up to supply voltage Vdd. When this condition occurs, FETs 21 and 23 conduct, thereby latching the complementary inverter output 17 up at the supply potential until the end of the clock pulse. When the clock pulse potential drops to ground potential, gating FET 13 turns on and clocking FET 21 turns off, forcing the output of the complementary inverter 14 to rapidly drop to ground potential while simultaneously turning off latching transistor 23

Search report of patent office

• No documents are cited as X or Y attack

Search result

Search strategies

Patent search

• Database used - Micropat

Note: Other databases will also be used to run these queries with the respective operators of the databases. Databases includes SIP, Google patents etc

Non patent search

Technical Articles

• Database used - Google scholar that covers IEEE
  • Years - 1985-1990

Magazine articles

• Found one relevant articles from BYTE magazine.
  • Gallium Arsenide Chips - Volume 9, issue 12 (November, 1984)

Non-Patents Analysis

Analysis 1

NAME	CLIP FET	A 15-ns CMOS 64K RAM
FIGURE
TYPE	Patent:- US5247212	IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-21, NO. 5
Title	Complementary logic input parallel (CLIP) logic circuit family	A 15-ns CMOS 64K RAM
Assignee	THUNDERBIRD TECH INC (US)	STANLEY E. SCHUSTER, MEMBER, IEEE, BARBARA A. CHAPPELL, MEMBEtt, IEEE, ROBERT L. FRANCH, PAUL F. GREH3R, STEPHEN P. KLEPNER, FANG-SHI J. LA1, MEMBER, IEEE, PETER W. COOK, MEMBER, IEEE, ROBERTA. LIPA, MEMBER, IEEE, REGINALD J. PERRY, WILLIAM F. POKORNY, AND MICHAEL A. ROBERGE
IPC	H01L21/8238; H01L27/092; H03K3/356; H03K19/0948; H03K19/096; H01L21/70; H01L27/085; H03K3/00; H03K19/0948; H03K19/096; (IPC1-7): H03K17/04; H03K19/003; H03K19/017; H03K19/094; H03K19/20
Priority date	19910131
Filing date	19910131
Publication date	9/21/1993	11/5/1986
Driving stage	P channel FET (CLIP AND gate) / N channel FET (CLIP OR gate)	N channel FET
Connection 1	FET being connected between a common output and a first potential level (Vdd)	FET being connected between a common output and GND
Connection 2	Control electrode of driving stage FET for receiving logic input signals (Multiple)	Control electrode of driving stage FET connected to higher order address lines
Gating stage	N channel FET (CLIP AND gate) / P channel FET (CLIP OR gate)	P channel FET
Connection 1	FET being connected between a second potential level (Ground or Vss) and common output.	FET being connected between a second potential level Vss and common output.
Connection 2	Control electrode of gating stage FET is connected to a control electrode of driving stage FET,	Control electrode of gating stage FET is directly/indirectly connected to driving stage which is not shown in figure. It is obvious as the working remains same
Complementary FET inverter	Complimentary P & N channel FETs	Complimentary P & N channel FETs
Connection 1	FET’s are serially connected between said first and second potential levels (Vdd and (Vss or grnd))	FET’s are serially connected between said first and second potential levels (Vdd and (Vss or grnd))
Connection 2	Inverter input being connected to common output.	Inverter input being connected to common output.
	Zg - channel width of gating transistors, Zd - channel width of driving transistors, I@*satd - saturation current for square channel driving transistor, I@*satg - saturation current for square channel gating transistor, Lg - channel length of gating transistors, Ld - channel length of driving stage transistors, and Sg - number of gating transistors	Since the connections are similar the channel width criteria remains same

Analysis 2

• Claim 21 - Germanium doped P-channel FET
• The document describes germanium doped P-channel FET for increasing the channel mobility (Page 2630)

Marked document

• 15-ns CMOS 64K RAM
• Germanium p-Channel MOSFET's with High Channel Mobility

Conclusion

• The article describes a similar driving stage, gating stage and inverter stage as shown in the above table. Only one extra stage for low order bits is added which is optional can be seen in the figure listed to the right side of above table shown as unmarked stage.
• Hence the article invalidates the inforce patent